1. Field of the Invention
The present invention relates to a memory circuit and more specifically such a circuit including a test arrangement for the memory. More particularly but not exclusively the memory circuit including built-in self-test circuitry.
2. Description of the Related Art
The increasing use of complex semiconductor chips creates problems for testing the functionality of those chips, and specifically in interfacing test equipment into the circuit.
Currently interest is centring upon the provision of embedded test circuitry, so-called xe2x80x9cbuilt-in self-test circuitryxe2x80x9d which, in exchange for a one-time investment in the circuitry allows ready access to the elements circuits and systems of interest at high speed.
One technique which is used is to apply inputs derived from a pseudo-random pattern generator as a write information to a memory and then to read from the memory into a multiple-input signature register. A controller associated with the pattern generator allow repeated loading of patterns into the memory followed by logging out into the signature register.
The signature register is a known device, also known as a compression register, which accumulates the responses such that any deviation in the final state of the register at the end of a test indicates both the presence of a defect in the memory and also an indication of the location of that defect.
It will of course be understood that provision of circuitry dedicated to built-in self-test occupies chip area and furthermore needs suitable connecting conductors in order to interface with the circuitry to be tested.
It is accordingly an object of the present invention to provide a circuit which at least partially mitigates the difficulties of the prior art.
According to the present invention there is provided a memory circuit having a plurality of complementary bitlines, a corresponding plurality of sense amplifiers for evaluating the logic state of said bitline pairs, each sense amplifier having an output, and a corresponding plurality of data latches for storing data to be written to said bitline pairs, wherein each data latch has an input and output, the circuit further comprising a respective multiplexer connected to each data latch input, a first input of said multiplexer being responsive to the output of a respective other data latch, and a second input of said multiplexer receiving said data to be written whereby in one state of said multiplexer said data latches are connected to form a test register.
Preferably at least one of said multiplexers have an input responsive to an output of the corresponding sense amplifier.
Preferably the circuit further comprises a corresponding plurality of logic circuits, each having an output connected to the first input of a respective one of said multiplexers, a first input receiving the output of said another data latch and a second input receiving said output of the corresponding sense amplifier.
According to a second aspect of the invention, there is provided a method of operating a memory circuit having plural complementary bitlines a corresponding plurality of sense amplifiers for evaluating the logic state of said bitline pairs, each sense amplifier having an output, and a corresponding plurality of data latches for storing data to be written to said bitline pairs, wherein each data latch has an input and output comprising: in one mode providing data to be written to said memory at an input of each said data latch, whereby said data is written to said memory in a test mode, connecting the input of each data latch to the output of a preceding data latch.
Advantageously the circuit is operable to provide, at the output of a last data latch, a signature output and each said logic circuit has a third input responsive to said signature output.